A 60GHz digitally-assisted power amplifier with 17.2dBm Psat, 11.3% PAE in 65nm CMOS

A digitally-assisted CMOS 60GHz PA is reported with high output power and improved power efficiency during power back-off. To combine large number of CMOS power transistors within compact area, a 2D distributed in-phase power combiner is utilized. Moreover, digitally-assisted self-tuning biasing is introduced for power back-off efficiency improvement, where DC power is reduced along with outputpower.

One digitally-assisted 4-way power-combined PA prototype was implemented in 65nm CMOS process with measured output power of 17.2dBm, PAE of 11.3%, and up to 170∼190% efficiency improvement during power back-off for the entire 7GHz band at 60GHz.

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