A 9-bit body-biased vernier ring time-to-digital converter in 65 nm CMOS technology

A high resolution Vernier Ring Time-to-digital Converter is presented in this paper. Body bias is applied to its delay cells to obtain a finer delay difference between two delay chains. The delay cells and arbiters are implemented in a ring structure, thus allowing a large input time interval to be measured. The digital circuit nature of this converter is also attractive for low power and small area design.

The simulation results reveal a 3 ps resolution, a −0.22/0.11 LSB differential nonlinearity (DNL) and a 9-bit range. The prototype chip is fabricated in 65 nm CMOS process consuming 0.44 mW with a 1.2 V power supply and occupies an area of 0.014 mm2.

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