Minimal hardware implementations of machine learning techniques have been attracting increasing interest over the last decades. In particular, FPGA implementations of neural networks are among the most appealing ones, given the match between system requirements and FPGA properties, namely parallelism and adaptation.
Here, we present a FPGA implementation of a conceptually simplified version of a recurrent neural network based on a single dynamical node subject to delayed feedback. We show that this configuration is capable of successfully performing simple real-time temporal patternclassification and chaotic time-series prediction