An energy-efficient switching scheme for a low-power successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. Taking the parasitic capacitance of the capacitor array into consideration, the average switching energy of the proposed scheme can be reduced by 97.4% compared with the conventional architecture. The proposed scheme also reduces the number of capacitors in the capacitor array by 75.5% and hence achieves area efficiency with high performance.
