This paper explains a fail-safe I/O circuit to control the RESET# pin of DDR3 SDRAM to achieve ultra-low power system operation. Conventional Fail-safe I/O circuits withstand conditions like hot plug, hot-insertion, hot-swapping and ensure IC reliability by limiting the current flowing into the I/O pin.
However they do not guarantee the functionality during supply-ramp cycles where the I/O supply is turned off while its output is pulled high externally. In case of RESET#, a small glitch on I/O pin can reset the DRAM chip. The fail-safe I/O circuit explained in this paper ensures smooth transition between ultra-lowpower suspension mode, where full chip supply is turned off, and normal operation mode.